Western Digital & Toshiba Separately Announce QLC 96-Layer NAND

 by Michael Rink

Both companies announced QLC, 96-Layer, FLASH memory chips on July 19th. Toshiba and Western Digital are both expecting 1.33Tb (terabits) of storage per chip. Western Digital’s announcement covers that the chip was jointly developed with Toshiba in Yokkaichi, Japan. However, Toshiba’s announcement makes no mention of Western Digital at all. Possibly a sign of lingering poor relations between the two companies despite it having been more than half a year since Toshiba dropped its 120 billion Yen lawsuit against Western Digital in December 2017. In any case, the differences between the two announcements are a significant divergence from their behavior when Toshiba first began publicly speaking about QLC technology in 2016.

QLC stands for quad-level cells and is the next step beyond the already common triple level cells (TLC). As the name indicates, QLC packs in 4 bits per cell, one more than TLC. Alongside packing in 33% more bits per cell (and twice as many possible states), we can reasonably expect a further decrease in write speeds and program-erase cycles as well as an increase in power consumption and error-rates; likely necessitating the development of new error-correcting code and controls. Unfortunately, neither company has been forthcoming with specifications for their new memory so we have very little idea what the exact rates or other specifications will eventually be.